6-1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright ?intersil corporation 1999 hi-5701/883 6-bit, 30 msps flash a/d converter description the hi-5701/883 is a monolithic, 6-bit, cmos flash analog- to-digital converter. it is designed for high speed applications where wide bandwidth and low power consumption are essential. its 30 msps speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit. the hi-5701/ 883 delivers 0.7 lsb differential nonlinearity while consuming only 250mw (typical) at 30 msps. microproces- sor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. an over?w bit is provided to allow the series connection of two converters to achieve 7-bit resolution. ordering information part number temperature range package hi1-5701t/883 -55 o c to +125 o c 18 lead cerdip features this circuit is processed in accordance to mil-std- 883 and is fully conformant under the provisions of paragraph 1.2.1. 30 msps with no missing codes 20mhz full power input bandwidth no missing codes over temperature sample and hold not required single +5v supply voltage cmos/ttl over?w bit applications video digitizing radar systems medical imaging communication systems high speed data acquisition systems june 1994 pinout hi-5701/883 (18 lead cerdip) top view 10 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 d4 1/2r d2 d1 d0 (lsb) v dd v in d3 v ref - d5 (msb) ovf v ss nc ce2 ce1 phase clk v ref + functional block diagram v dd v ss 2 (sample) clk 7 12 3 phase 8 v in r/2 r/2 1/2r comparator latches d cl q d cl q d cl q d cl q d cl q d cl q overflow (ovf) d5 (msb) d4 d3 d2 d1 d0 (lsb) ce1 ce2 ? 2 ? 1 ? 1 ? 1 ? 2 comp comp r d cl q r r r r v ref - and encoder logic v ref + 64 63 r 10 16 11 9 16 15 3 4 5 10 11 2 1 comp 32 comp 2 comp 1 1 (auto balance) spec number 512031 file number 3378
6-2 hi-5701/883 pin description pin # name description 1 d5 bit 6, output (msb) 2 ovf over?w, output 3v ss digital ground 4 nc no connection 5 ce2 three-state output enable input, active high (see truth table) 6 ce1 three-state output enable input, active low (see truth table) 7 clk clock input 8 phase sample clock phase control input. when phase is low, sample unknown ( 1) occurs when the clock is low and auto balance ( 2) occurs when the clock is high (see phase control table) 9v ref + reference voltage positive input 10 v ref - reference voltage negative input 11 v in analog signal input 12 v dd power supply, +5v 13 d0 bit 1, output (lsb) 14 d1 bit 2, output 15 d2 bit 3, output 16 1/2r reference ladder midpoint 17 d3 bit 4, output 18 d4 bit 5, output chip enable truth table ce1 ce2 d0 - d5 ovf 0 1 valid valid 1 1 three - state valid x 0 three - state three - state x = don? care. phase control clock phase internal generation 0 0 sample unknown ( 2) 0 1 auto balance ( 1) 1 0 auto balance ( 1) 1 1 sample unknown ( 2) spec number 512031
6-3 absolute maximum ratings thermal information supply voltage, v dd to v ss . . . . . . . . . . . (v ss - 0.5) < v dd < +7.0v analog and reference input pins. .(v ss - 0.5) < v ina < (v dd +0.5v) digital i/o pins . . . . . . . . . . . . . . . . (v ss - 0.5) < v i/o < (v dd +0.5v) operating temperature range hi1-5701t/883 . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c storage temperature range . . . . . . . . . . . . . . . - 65 o c to +150 o c lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300 o c esd clasi?ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance ja jc hi1-5701t/883. . . . . . . . . . . . . . . . . . . . . 70 0 c/w 28 o c/w power dissipation at +75 o c (note 1) hi1-5701t/883. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4mw power dissipation derating factor above +75 o c hi1-5701t/883. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14mw/ o c reliability information transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4815 worst case density . . . . . . . . . . . . . . . . . . . . . . . . 3.05 x 10 4 a/cm 2 caution: stresses above those listed in ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. table 1. dc electrical performance characteristics device tested at: v dd = +5.0v; v ref + = +4.0v; v ref - = v ss = gnd; f s = speci?d clock frequency at 50% duty cycle; c l = 30pf; unless otherwise speci?d. parameters symbol conditions group a subgroup temperature limits unit min max accuracy integral linearity error (best fit method) inl f s = 20mhz, f in = dc 1 +25 o c- 1.25 lsb 2, 3 +125 o c, -55 o c- 2.0 lsb f s = 30mhz, f in = dc 1 +25 o c- 1.5 lsb 2, 3 +125 o c, -55 o c- 2.5 lsb differential linearity error (guaranteed no missing codes) dnl f s = 20mhz, f in = dc 1 +25 o c- 0.6 lsb 2, 3 +125 o c, -55 o c- 0.75 lsb f s = 30mhz, f in = dc 1 +25 o c- 0.75 lsb 2, 3 +125 o c, -55 o c- 1.0 lsb offset error (adjustable to zero) vos f s = 20mhz, f in = dc 1 +25 o c- 2.0 lsb 2, 3 +125 o c, -55 o c- 2.5 lsb full scale error (adjustable to zero) fse f s = 20mhz, f in = dc 1 +25 o c- 2.0 lsb 2, 3 +125 o c, -55 o c- 2.5 lsb analog input analog input resistance r in v in = 4v 1 +25 o c4-m ? 2, 3 +125 o c, -55 o c4 - m ? analog input bias current i b v in = 0v, 4v 1 +25 o c 1.0 a 2, 3 +125 o c, -55 o c 1.0 a reference input total reference resistance r l 1 +25 o c 250 - ? 2, 3 +125 o c, -55 o c 235 - ? speci?ations hi-5701/883 spec number 512031
6-4 speci?ations hi-5701/883 digital inputs input high voltage v ih 1 +25 o c 2.0 - v 2, 3 +125 o c, -55 o c 2.0 - v input low voltage v il 1 +25 o c - 0.8 v 2, 3 +125 o c, -55 o c - 0.8 v logic input current i in v in = 0v, +5v 1 +25 o c- 1 a 2, 3 +125 o c, -55 o c- 1 a digital outputs output leakage i oz ce2 = 0v, v o = 0v, 5v 1 +25 o c- 1.0 a 2, 3 +125 o c, -55 o c- 1.0 a output logic source current i oh v o = 4.5v 1 +25 o c -3.2 - ma 2, 3 +125 o c, -55 o c -3.2 - ma output logic sink current i ol v o = 0.4v 1 +25 o c 3.2 - ma 2, 3 +125 o c, -55 o c 3.2 - ma power supply rejection offset error psrr ? vos v dd = 5v 10% 1 +25 o c- 1.0 lsb 2, 3 +125 o c, -55 o c- 1.5 lsb gain error psrr ? fse v dd = 5v 10% 1 +25 o c- 1.0 lsb 2, 3 +125 o c, -55 o c- 1.5 lsb power supply current supply current i dd f s = 30mhz 1 +25 o c - 60 ma 2, 3 +125 o c, -55 o c - 75 ma note: 1. dissipation rating assumes device is mounted with all leads soldered to printed circuit board. table 1. dc electrical performance characteristics (continued) device tested at: v dd = +5.0v; v ref + = +4.0v; v ref - = v ss = gnd; f s = speci?d clock frequency at 50% duty cycle; c l = 30pf; unless otherwise speci?d. parameters symbol conditions group a subgroup temperature limits unit min max spec number 512031
6-5 speci?ations hi-5701/883 table 2. ac electrical performance characteristics device tested at: v dd = +5.0v; v ref + = +4.0v; v ref - = v ss = gnd; f s = speci?d clock frequency at 50% duty cycle; c l = 30pf; unless otherwise speci?d. parameter symbol conditions group a subgroup temperature limits unit min max maximum conversion rate no missing codes 9 +25 o c 30 - msps 10, 11 +125 o c, -55 o c 30 - msps data output enable time t en 9 +25 o c - 20 ns 10, 11 +125 o c, -55 o c - 20 ns data output disable time t dis 9 +25 o c - 20 ns 10, 11 +125 o c, -55 o c - 20 ns data output delay t od 9 +25 o c - 20 ns 10, 11 +125 o c, -55 o c - 20 ns data output hold t h 9 +25 o c10-ns 10, 11 +125 o c, -55 o c5 - ns table 3. electrical performance characteristics (note 1) device characterized at: v dd = +5.0v; v ref + = +4.0v; v ref - = v ss = gnd; f s = speci?d clock frequency at 50% duty cycle; c l = 30pf; unless otherwise speci?d. parameter symbol conditions temperature limits unit min max minimum conversion rate no missing codes +25 o c, +125 o c, -55 o c - 0.125 msps note: 1. parameters listed in table 3 are controlled via design or process parameters and are not directly tested at ?al production. these param- eters are lab characterized upon initial design release, or upon design changes. these parameters are guaranteed by characteriz ation based upon data from multiple production runs which re?ct lot to lot and within lot variation. table 4. electrical test requirements mil-std-883 test requirements subgroups (see tables 1 and 2) interim electrical parameters (pre burn-in) 1 final electrical test parameters 1 (note 1), 2, 3, 9, 10, 11 group a test requirements 1, 2, 3, 9, 10, 11 groups c and d endpoints 1 note: 1. pda applies to subgroup 1 only. no other subgroups are included in pda. spec number 512031
6-6 hi-5701/883 die characteristics die dimensions: 2220 m x 3320 m x 19 1mils metallization: type: si - al thickness: 11k ? 1k ? glassivation: type: sio 2 thickness: 8k ? 1k ? die attach: material: gold silicon eutectic alloy temperature: ceramic dip - 460 o c (max) worst case current density: 3.05 x 10 4 a/cm 2 metallization mask layout hi-5701/883 v ss ovf d5 d4 d3 1/2r d2 d1 d0 v dd v ss ce2 ce1 clk phase v ref + v ref - v in v dd spec number 512031
6-7 hi-5701/883 spec number 512031 timing waveforms figure 1. input-to-output timing figure 2. output enable timing burn-in circuit hi-5701/883 cerdip notes: 1. power supply and the reference voltage input to be decoupled by 0.01 f in parallel with 1 f capacitor 2. clock input is a pulse with 1:10 duty cycle, approximately 100khz and 0v to 4v amplitude 3. v in , analog input is a slow triangular waveform (f in = 10khz) and 0v to 4v amplitude 4. all supplies to be protected with <7v zener diodes n - 2 t ap t aj t h t od data n - 4 data n-3 data n-2 data n-1 data n clock input analog input data output sample auto balance t ab sample n - 1 auto balance sample n auto balance sample n + 1 auto balance sample n + 2 phase - low comparator data is latched encoded data is latched into the output registers clock input phase - high ? 2 ? 2 ? 2 ? 2 ? 2 ? 1 ? 1 ? 1 ? 1 ce1 ce2 d0 - d5 ovf t dis t en t dis t en high impedance high impedance data data data data data high impedance 10 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 c7 0.01 f/0.1 f cap cap c1 0.01 f/0.1 f +5v 0v clk +4v 0v v in
6-8 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com hi-5701/883 packaging frit seal dual-in-line ceramic package bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa c a - b m d s s ccc c a - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m f18.3 mil-std-1835 gdip1-t18 (d-6, configuration a) 18 lead frit seal dual-in-line ceramic package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.960 - 24.38 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.070 0.38 1.78 6 s1 0.005 - 0.13 - 7 s2 0.005 - 0.13 - 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n18 188 notes: 1. index area: a notch or a pin one identi?ation mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer s identi?ation shall not be used as a pin one identi?ation mark. 2. the maximum limits of lead dimensions b and c or m shall be mea- sured at the centroid of the ?ished lead surfaces, when solder dip or tin plate lead ?ish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and ?ish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be con?ured with a partial lead paddle. for this con?uration dimension b3 replaces dimension b1. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. spec number 512031
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